// Copyright (C) 1953-2022 NUDT
// Verilog module name - management_interface_hub
// Version: V3.4.0.20220225
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         command interface transfer
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module management_interface_hub
#(
	parameter PORT_NUM = 21, // 16 gmac+ 4 xgmac+ 1 hcp
              INDEX_HCP= 20	
)
    (
        i_clk,
        i_rst_n,

        iv_command,   
        i_command_wr,           
        
        ov_addr,
        ov_wdata,    

        o_wr_ffi,
        o_rd_ffi,
        o_wr_dex,
        o_rd_dex,
        o_wr_ctx,
        o_rd_ctx,

        o_wr_flt   ,
        o_rd_flt   ,
        
        o_wr_pcb   ,
        o_rd_pcb   ,
        
        o_wr_trl   ,
        o_rd_trl   ,
        
        o_wr_idc   ,
        o_rd_idc   ,
        
        o_wr_ist   ,
        o_rd_ist   ,

        o_wr_qgc  ,
        o_rd_qgc  ,
                   
        o_wr_mac  ,
        o_rd_mac  , 

        o_wr_tau     ,
        o_rd_tau     ,        

        i_wr_ffi,
        iv_addr_ffi,
        iv_rdata_ffi,

        i_wr_dex,
        iv_addr_dex,
        iv_rdata_dex,

        i_wr_ctx,
        iv_addr_ctx,
        iv_rdata_ctx,

        i_wr_pcb,
        iv_addr_pcb,
        iv_rdata_pcb,

        i_wr_flt,
        iv_addr_flt,
        iv_rdata_flt,
        
        i_wr_trl,
        iv_addr_trl,
        iv_rdata_trl, 

        i_wr_idc,
        iv_addr_idc,
        iv_rdata_idc, 

        i_wr_ist,
        iv_addr_ist,
        iv_rdata_ist,        

        i_wr_qgc,
        iv_addr_qgc,
        iv_rdata_qgc,

        i_wr_mac     ,
        iv_addr_mac  ,
        iv_rdata_mac ,  

        i_wr_tau        ,
        iv_addr_tau     ,
        iv_rdata_tau    ,         

        o_command_ack_wr,
        ov_command_ack,
 
        ov_tss_ver                             ,                   
        ov_hpriority_be_police_threshold                  ,
        ov_rc_police_threshold                  ,
        ov_lpriority_be_police_threshold         ,
        o_qbv_or_qch                           ,
        ov_time_slot_length                    ,
        ov_schedule_period                        
    ); 
// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n; 
//receive command           
input       [63:0]      iv_command;   
input                   i_command_wr;           
  
output      [18:0]      ov_addr;
output      [31:0]      ov_wdata;
//to all                  
output      [PORT_NUM-1:0]      o_wr_ffi;
output      [PORT_NUM-1:0]      o_rd_ffi;
output      [PORT_NUM-1:0]      o_wr_dex;
output      [PORT_NUM-1:0]      o_rd_dex;
output      [PORT_NUM-1:0]      o_wr_ctx;
output      [PORT_NUM-1:0]      o_rd_ctx;
//to flt                
output                  o_wr_flt;
output                  o_rd_flt;
//to pcb                
output                  o_wr_pcb;
output                  o_rd_pcb;

output                  o_wr_trl;
output                  o_rd_trl;
        
output                  o_wr_idc;
output                  o_rd_idc;
        
output                  o_wr_ist;
output                  o_rd_ist;
//to qgc                
output      [PORT_NUM-2:0]            o_wr_qgc;
output      [PORT_NUM-2:0]            o_rd_qgc;

output      [PORT_NUM-2:0]            o_wr_mac  ;
output      [PORT_NUM-2:0]            o_rd_mac  ; 
            
output                  o_wr_tau     ;
output                  o_rd_tau     ;
//from ffi_p8 
input        [PORT_NUM-1:0]           i_wr_ffi;
input        [PORT_NUM*19-1:0]     iv_addr_ffi;
input        [PORT_NUM*32-1:0]     iv_rdata_ffi;
//from dex_p8 
input        [PORT_NUM-1:0]           i_wr_dex;
input        [PORT_NUM*19-1:0]     iv_addr_dex;
input        [PORT_NUM*32-1:0]     iv_rdata_dex;
//from ctx_p8 
input        [PORT_NUM-1:0]           i_wr_ctx;
input        [PORT_NUM*19-1:0]     iv_addr_ctx;
input        [PORT_NUM*32-1:0]     iv_rdata_ctx;
//from pcb 
input                   i_wr_pcb;
input        [18:0]     iv_addr_pcb;
input        [31:0]     iv_rdata_pcb;
//from flt 
input                   i_wr_flt;
input        [18:0]     iv_addr_flt;
input        [31:0]     iv_rdata_flt;
//from trl 
input                   i_wr_trl;
input        [18:0]     iv_addr_trl;
input        [31:0]     iv_rdata_trl;
//from idc 
input                   i_wr_idc;
input        [18:0]     iv_addr_idc;
input        [31:0]     iv_rdata_idc;
//from ist 
input                   i_wr_ist;
input        [18:0]     iv_addr_ist;
input        [31:0]     iv_rdata_ist;
//from qgc 
input        [(PORT_NUM-1)-1:0]           i_wr_qgc;
input        [(PORT_NUM-1)*19-1:0]     iv_addr_qgc;
input        [(PORT_NUM-1)*32-1:0]     iv_rdata_qgc;

input        [(PORT_NUM-1)-1:0]           i_wr_mac  ;
input        [(PORT_NUM-1)*19-1:0]     iv_addr_mac  ;
input        [(PORT_NUM-1)*32-1:0]     iv_rdata_mac ;

input                   i_wr_tau        ;
input        [18:0]     iv_addr_tau     ;
input        [31:0]     iv_rdata_tau    ; 
 
output                  o_command_ack_wr;
output       [63:0]     ov_command_ack; 

output      [31:0]      ov_tss_ver                      ;
output      [8:0]       ov_hpriority_be_police_threshold           ; 
output      [8:0]       ov_rc_police_threshold           ;
output      [8:0]       ov_lpriority_be_police_threshold  ; 
output                  o_qbv_or_qch          ;
output      [10:0]      ov_time_slot_length   ;
output      [10:0]      ov_schedule_period    ;   
//to grm                
wire                    w_wr_cpa2grm;
wire                    w_rd_cpa2grm;
//from grm 
wire                    w_wr_grm2cag     ;
wire         [18:0]     wv_addr_grm2cag  ;
wire         [31:0]     wv_rdata_grm2cag ;	
tss_command_parse 
#(.INDEX_HCP(INDEX_HCP), .PORT_NUM(PORT_NUM) )
tss_command_parse(
.i_clk        (i_clk       ),
.i_rst_n      (i_rst_n     ),

.iv_command   (iv_command  ),   
.i_command_wr (i_command_wr),           

.ov_addr      (ov_addr     ),
.ov_wdata     (ov_wdata    ),

.o_wr_ffi  (o_wr_ffi  ),
.o_rd_ffi  (o_rd_ffi  ),
.o_wr_dex  (o_wr_dex  ),
.o_rd_dex  (o_rd_dex  ),

.o_wr_grm     (w_wr_cpa2grm     ),
.o_rd_grm     (w_rd_cpa2grm     ),

.o_wr_flt     (o_wr_flt     ),
.o_rd_flt     (o_rd_flt     ),

.o_wr_pcb     (o_wr_pcb     ),
.o_rd_pcb     (o_rd_pcb     ),

.o_wr_trl     (o_wr_trl     ),
.o_rd_trl     (o_rd_trl     ),
                            
.o_wr_idc     (o_wr_idc     ),
.o_rd_idc     (o_rd_idc     ),        
                            
.o_wr_ist     (o_wr_ist     ),
.o_rd_ist     (o_rd_ist     ),	

.o_wr_qgc    (o_wr_qgc    ),
.o_rd_qgc    (o_rd_qgc    ),

.o_wr_mac  (o_wr_mac  ),
.o_rd_mac  (o_rd_mac  ), 

.o_wr_tau     (o_wr_tau     ),
.o_rd_tau     (o_rd_tau     )  
); 
tss_commandack_generate tss_commandack_generate_inst(
.i_clk                                      (i_clk            ),
.i_rst_n                                    (i_rst_n          ),          

.o_command_ack_wr                           (o_command_ack_wr ),
.ov_command_ack                             (ov_command_ack   ),

.i_wr_ffi                                (i_wr_ffi             ),
.iv_addr_ffi                             (iv_addr_ffi          ),
.iv_rdata_ffi                            (iv_rdata_ffi         ),

.i_wr_dex                                (i_wr_dex             ),
.iv_addr_dex                             (iv_addr_dex          ),
.iv_rdata_dex                            (iv_rdata_dex         ),

.i_wr_ctx                                (i_wr_ctx             ),
.iv_addr_ctx                             (iv_addr_ctx          ),
.iv_rdata_ctx                            (iv_rdata_ctx         ),

.i_wr_grm                                   (w_wr_grm2cag                ),
.iv_addr_grm                                (wv_addr_grm2cag             ),
.iv_rdata_grm                               (wv_rdata_grm2cag            ),

.i_wr_pcb                                   (i_wr_pcb                ),
.iv_addr_pcb                                (iv_addr_pcb             ),
.iv_rdata_pcb                               (iv_rdata_pcb            ),

.i_wr_flt                                   (i_wr_flt                ),
.iv_addr_flt                                (iv_addr_flt             ),
.iv_rdata_flt                               (iv_rdata_flt            ),

.i_wr_trl                                   (i_wr_trl                ),
.iv_addr_trl                                (iv_addr_trl             ),
.iv_rdata_trl                               (iv_rdata_trl            ),

.i_wr_idc                                   (i_wr_idc                ),
.iv_addr_idc                                (iv_addr_idc             ),
.iv_rdata_idc                               (iv_rdata_idc            ),

.i_wr_ist                                   (i_wr_ist                ),
.iv_addr_ist                                (iv_addr_ist             ),
.iv_rdata_ist                               (iv_rdata_ist            ),

.i_wr_qgc                                  (i_wr_qgc               ),
.iv_addr_qgc                               (iv_addr_qgc            ),
.iv_rdata_qgc                              (iv_rdata_qgc           ),

.i_wr_mac                                (i_wr_mac     ),
.iv_addr_mac                             (iv_addr_mac  ),
.iv_rdata_mac                            (iv_rdata_mac ),  
 
.i_wr_tau                                   (i_wr_tau        ),
.iv_addr_tau                                (iv_addr_tau     ),
.iv_rdata_tau                               (iv_rdata_tau    )
); 
global_registers_management global_registers_management_inst(
.i_clk                            (i_clk                                 ),                
.i_rst_n                          (i_rst_n                               ),      
                                                                         
.iv_addr                          (ov_addr                       ),         
.iv_wdata                         (ov_wdata                      ), 

.i_wr                             (w_wr_cpa2grm                          ),      
.i_rd                             (w_rd_cpa2grm                          ),                                                                                      
.o_wr                             (w_wr_grm2cag                          ),      
.ov_addr                          (wv_addr_grm2cag                       ),      
.ov_rdata                         (wv_rdata_grm2cag                      ),      

.ov_tss_ver                          (ov_tss_ver                           ),
.ov_hpriority_be_police_threshold               (ov_hpriority_be_police_threshold                ), 
.ov_rc_police_threshold               (ov_rc_police_threshold                ),
.ov_lpriority_be_police_threshold      (ov_lpriority_be_police_threshold                 ),
.o_qbv_or_qch                        (o_qbv_or_qch                                   ),          
.ov_time_slot_length                 (ov_time_slot_length                            ),   
.ov_schedule_period                  (ov_schedule_period                             )     
);   
endmodule
